So privileged to be a part of the #SERB Sponsord High-End Workshop (Karyashala) on ‘Machine Learning based High Performance and Low Power VLSI System Design using FPGA’ , organized by the Dept. of ECE, Indian Institute of Information Technology, Tiruchirappalli, Sethurapatti, Tamil Nadu.

I handled the modules ‘#Hardware for #DeepLearning‘ and ‘#FPGA#Architecture and #DesignFlows‘. Happy to give some inputs to the participants on Complexity Reduction Techniques in Convolution operations, FPGA Design flow using #VitisHLS, #Python + #DPU based approach using #VitisAI, #PYNQ, and #MATLAB for FPGA. AKSHAYRAJ M.R handled sessions on ‘#Computing#Convolutions‘ and ‘#RTL_Design‘.

Happy to get connected with many research scholars from various institutions in the country, including National Institute of Technology Puducherry, National institute of technology calicut, Vellore Institute of Technology, Madras Institute Of Technology – MIT Chennai, Anna University, etc.

Thanking Dr.G.Lakshminarayanan Sir, my Research Guide and Senior Professor, Dept.of ECE, National Institute of Technology Tiruchirappalli for giving the Opportunity and Dr.Senthil Sivakumar M, Asst.Professor, Dept.of ECE, IIIT Trichy for the nice hospitality.

#FPGA#HLS#ZYNQ#PYNQ#Hardware#deeplearning#machinelearning