Another fruitful day with the students of the College of Engineering Vadakara. Completed the second part of the Hands on Workshop on #FPGA#Architecture and #Programming with AKSHAYRAJ M.R . Today we discussed the #FPGA_Design with #VitisHLS.

High-level synthesis (HLS) is a technology that assists with the transformation of a behavioral description of hardware into an RTL model. It is considered to be part of an electronic system level (ESL) design flow.

Vitis #HLS (formerly #Xilinx Vivado HLS) is a High-Level Synthesis (HLS) tool developed by Xilinx and available at no cost. Vitis HLS allows the user to easily create complex FPGA-based algorithms using #C/C++ code.Shared the FPGA design flow with Vivado and Vitis HLS tools and implemented the design on #ZYBO (Zynq 7000) and #Pynq Z2 boards.

Happy to get connected with the young minds passionate about their career in hardcore #electronics domain (instead of running behind software/IT sector) and working hard to make it possible. Thanks to Ragi Rg Chechi (Asst. Professor, Dept. of ECE) and Junaid (Lab Assistant, Dept. Of ECE) for the supports.

#FPGA
#Xilinx
#VITIS#HLS
#VIVADO#verilog
#electronics